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March 1997
ML4830* Electronic Ballast Controller
GENERAL DESCRIPTION
The ML4830 is a complete solution for a dimmable, high power factor, high efficiency electronic ballast. Contained in the ML4830 are controllers for "boost" type power factor correction as well as for a dimming ballast. The Power factor circuit uses the average current sensing method with a gain modulator and over-voltage protection. This system produces power factors of better than 0.99 with low input current THD at > 95% efficiency. Special care has been taken in the design of the ML4830 to increase system noise immunity by using a high amplitude oscillator, and a gain modulator. An overvoltage protection comparator stops the PFC section in the event of sudden load decrease. The ballast section provides for programmable starting scenarios with programmable preheat and lamp out-ofsocket interrupt times. The IC controls lamp output through either frequency or Pulse Width control using lamp current feedback. The ML4830 is designed using Micro Linear`s SemiStandard tile array methodology. Customized versions of this IC, optimized to specific ballast architectures can be made available. Contact Micro Linear or an authorized representative for more information.
FEATURES
s
Complete Power Factor Correction and Dimming Ballast Control on one IC Low Distortion, High Efficiency Continuous Boost, Average Current sensing PFC section Programmable Start Scenario for Rapid or Instant Start Lamps Selectable Variable Frequency dimming and starting Programmable Restart for lamp out condition to reduce ballast heating Over-Temperature Shutdown replaces external heat sensor for safety PFC Over-Voltage comparator eliminates output "runaway" due to load removal Large oscillator amplitude and gain modulator improves noise immunity
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*This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
MODE 7 9 R(SET) R(T)/C(T) OSCILLATOR LAMP F.B. LFB OUT 8 5 6
OUTPUT DRIVERS 12 10 R(X)/C(X) INTERRUPT PRE-HEAT AND INTERRUPT TIMERS PWM OR FREQUENCY MODULATOR OUT B OUT A 15
14
11 2 1 4 3 20 19
OVP/INHIBIT IA OUT IA- IA+/I(LIM) I(SINE) EA OUT EA- POWER FACTOR CONTROLLER UNDER-VOLTAGE AND THERMAL SHUTDOWN
PFC OUT
16
VCC VREF GND
17 18 13
1
ML4830
PIN CONFIGURATION
ML4830 20-PIN PDIP (P20)
IA- IA OUT I(SINE) IA+/I(LIM) LAMP F.B. LFB OUT R(SET) MODE R(T)/C(T) INTERRUPT
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
ML4830 20-PIN PDIP (P20)
EA OUT EA- VREF VCC PFC OUT OUT A OUT B GND R(X)/C(X) OVP/INHIBIT
IA- IA OUT I(SINE) IA+/I(LIM) LAMP F.B. LFB OUT R(SET) MODE R(T)/C(T) INTERRUPT
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
EA OUT EA- VREF VCC PFC OUT OUT A OUT B GND R(X)/C(X) OVP/INHIBIT
TOP VIEW
TOP VIEW
PIN DESCRIPTION
PIN# NAME FUNCTION PIN# NAME FUNCTION
1 2 3 4
IA- IA OUT I(SINE) IA+/I(LIM)
Inverting input of the PFC average current error amplifier Output and compensation node of the PFC average current error amplifier PFC gain modulator input Non-Inverting input of the PFC average current error amplifier and input of peak current limit comparator Inverting input of an Error Amplifier used to sense (and regulate) lamp arc current. Also the input node for dimming control Output from the Lamp Current Error Amplifier used for lamp current loop compensation External resistor which sets oscillator FMAX, and R(X)/C(X) charging current Controls how the Lamp Current Error Amp and preheat timers modulate the ballast outputs. Two Variable Frequency and 1 PWM mode are available through this pin Oscillator timing components
11 OVP/ INHIBIT
When the voltage of this pin exceeds 5V, the PFC output is inhibited. When the voltage exceeds 6.7V, the IC function is inhibited and the IC is reset. This pin can be used for a remote ballast shutdown. Sets the timing for the preheat, dimming lockout and interrupt IC Ground Ballast MOSFET drive output Ballast MOSFET drive output Power Factor MOSFET drive output Positive Supply for the IC Buffered output for the 7.5V voltage reference Inverting input to PFC error amplifier PFC Error Amplifier output and compensation node
12 R(X)/C(X) 13 GND 14 OUT B 15 OUT A 16 PFC OUT 17 VCC 18 VREF 19 EA- 20 EA OUT
5
LAMP F.B.
6
LFB OUT
7 8
R(SET) MODE
9
R(T)/C(T)
10 INTERRUPT A voltage of greater than VREF resets the chip and causes a restart after a delay of 3 times the start interval. Used for lamp-out detection and restart
2
ML4830
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current (ICC) ............................................... 75mA Output Current, Source or Sink (Pins 14) DC ................................................................... 250mA Output Energy (capacitive load per cycle).............. 1.5 mJ Gain Modulator I(SINE) Input (Pin 3) ..................... 10 mA Amplifier Source Current (Pin 6, 20) ...................... 50 mA Analog Inputs (Pins 1, 5, 10, 11, 19) .... -0.3V to VCC -2V Pin 4 input voltage ........................................... -3V to 5V Junction Temperature ............................................ 150C Storage Temperature Range ................... -65C to +150C Lead Temperature (Soldering 10 Sec.) .................. +260C Thermal Resistance (qJA) Plastic DIP-P ................................................... 65C/W Plastic SOIC ..................................................... 80C/W
OPERATING CONDITIONS
Temperature Range ML4830C .................................................. 0C to 85C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, R(SET) = 26kW, R(T) = 52.3kW, C(T) = 470pF, TJ = Junction Operating Temperature Range, ICC = 25mA
PARAMETER Amplifiers (Pins 1, 2, 5, 6, 19, 20) Input Offset Voltage Input Bias Current Open Loop Gain PSRR Output Low Output High Source Current Sink Current VOUT = 7V VOUT = 1.5V VOUT = 0.2V Slew Rate Unity Gain Bandwidth Gain Modulator Output Voltage (Note 1) ISINE = 100A, VPIN20 = 3V ISINE = 300A, VPIN20 = 3V ISINE =100A, VPIN20 = 6V ISINE = 300A, VPIN20 = 6V Output Voltage Limit Offset Voltage ISINE = 600A, VPIN19 = 0V ISINE = 0, VPIN19 = 0V ISINE = 150A, VPIN19 = 8V I(SINE) Input Voltage
Note 1:
CONDITIONS
MIN
TYP
MAX
UNITS
3.0 -0.3 65 VCCZ - 3V < VCC < VCCZ - 0.5V 70 0 7.2 -4 5 10 1.5 3.0 7.5 -7 10 90 100
10.0 -1.0
mV A dB dB
0.5
V V mA mA A V/s MHz
80 255 220 660 0.88 15 15 0.8 1.4 1.8
mV mV mV mV V mV mV V
ISINE = 200A
Measured at Pin 1 with Pins 1 and 2 shorted together and Pin 4 at GND.
3
ML4830
ELECTRICAL CHARACTERISTICS
PARAMETER Oscillator Initial accuracy Voltage stability Temperature stability Total Variation Ramp Valley to Peak C(T) Charging Current (FM Modes) VPIN8 = 0V, VPIN9 = 2.5V, VPIN12 = 0.9V, Preheat VPIN8 = 0V, VPIN9 = 2.5V, Max. dimming C(T) Discharge Current Output Drive Deadtime R(SET) Voltage Reference Section Output Voltage Line regulation Load regulation Temperature stability Total Variation Output Noise Voltage Long Term Stability Short Circuit Current Line, load, temp 10Hz to 10KHz TJ = 125C, 1000 hrs VCC < VCCZ - 0.5V, VREF = 0V 7.35 50 5 -40 TA = 25C, IO = 1mA VCCZ - 3V < VCC , VCCZ - 0.5V 1mA < IO < 20mA 7.4 7.5 2 2 0.4 7.65 7.6 10 15 V mV mV % V V mV mA VPIN8 = 0V, VPIN9 = 2.5V Line, temperature 68 2.5 -94 -188 5 0.2 2.5 TA = 25C, PWM or Dimming Lockout VCCZ - 3V < VCC (Continued)
CONDITIONS MIN TYP MAX UNITS
Preheat and Interrupt Timer (Pin 10) (R(X) = 590Ky, C(X) = 5.6F) Initial Preheat Period Subsequent Preheat Period Start Period Interrupt Period Pin 12 Charging Current Pin 12 Open Circuit Voltage Pin 12 Maximum Voltage Input Bias Current Preheat Lower Threshold Preheat Upper Threshold Interrupt Recovery Threshold Start Period End Threshold VPIN12 = 1.2V VCC = 12.3V in UVLO 0.4 7.0 0.8 0.7 2.1 6.3 -23 0.9 7.3 -0.1 1.18 3.36 1.18 6.6 1.1 7.7 s s s s A V V A V V V V
4
ML4830
ELECTRICAL CHARACTERISTICS
PARAMETER OVP/Inhibit Comparator (Pin 11) OVP Threshold Hysteresis Input Bias Current Propagation Delay Shutdown Threshold Shutdown Hysteresis PWM Comparator (PWM Mode) Start Period Duty Cycle Outputs Output Voltage Low IOUT = 20mA IOUT = 200mA Output Voltage High IOUT = -20mA IOUT = -200mA Output Voltage Low in UVLO Output Rise/Fall Time Under-Voltage Lockout and Bias Circuits IC Shunt Voltage (VCCZ) VCCZ Load Regulation VCCZ Total Variation Start-up Current Operating Current Start-up Threshold Shutdown Threshold Shutdown Temperature (TJ) Hysteresis (TJ) ICC = 25mA 25mA < ICC < 68mA Load, Temp VCC - 12.3V VCC = VCCZ - 0.5V 12.4 1.3 15 VCCZ - 0.5 VCCZ - 3.5 120 30 12.8 13.5 150 14.2 300 14.6 1.7 19 V mV V mA mA V V C C IOUT = 10mA, VCC = 8V CL = 1000pF VCC - 2.5 VCC - 3.0 0.4 2.1 VCC - 1.9 VCC - 2.2 0.8 50 1.5 0.8 3.0 V V V V V ns 40 50 60 % 6.36 0.7 4.87 5.0 0.5 -0.3 500 6.7 1.2 7.04 1.7 -2 5.13 V V A ns V V
(Continued)
CONDITIONS MIN TYP MAX UNITS
FUNCTIONAL DESCRIPTION
OVERVIEW The ML4830 consists of an Average Current controlled continuous boost Power Factor front end section with a flexible ballast control section. Start-up and lamp-out retry timing are controlled by the selection of external timing components, allowing for control of a wide variety of different lamp types. The ballast control section can be set up to adjust lamp power using either Pulse Width (PWM) or frequency modulation (FM). Either non-overlapping or overlapping conduction can be selected for the FM mode. This allows for the IC to be used with a variety of different ouput networks.
POWER FACTOR SECTION The ML4830 Power Factor section is an average current sensing boost mode PFC control circuit which is architecturally similar to that found in the ML4821. For detailed information on this control architecture, please refer to Application Note 16 and the ML4821 data sheet. GAIN MODULATOR The ML4830 gain modulator provides high immunity to the disturbances caused by high power switching. The rectified line input sine wave is converted to a current via a dropping resistor. In this way, small amounts of ground noise produce an insignificant effect on the reference to the PWM comparator.
5
ML4830
The output of the gain modulator appears as a voltage across the 14K resistor (Figure 1) on the positive terminal of IA to form the reference for the current error amplifier. When the loop is in regulation, the negative voltage on IA+/I(LIM) (Pin 4) keeps the positive terminal of IA at 0V. OVERVOLTAGE PROTECTION AND INHIBIT The OVP/INHIBIT pin serves to protect the power circuit from being subjected to excessive voltages if the load should change suddenly (lamp removal). A divider from the high voltage DC bus (Figure 8: R14, R24) sets the OVP trip level. When the voltage on Pin 11 exceeds 5V, the PFC transistor is inhibited. The ballast section will continue to operate. If Pin 11 is driven above 6.8V, the IC is inhibited and goes into the low quiescent mode. The OVP threshold should be set to a level where the power components are safe to operate, but not so low as to interfere with the boost voltage regulation loop (R11, R12, R23). BALLAST OUTPUT SECTION The IC controls output power to the lamps in one of three different modes. The Mode pin (Pin 8) sets the operating mode of the IC. With Pin 8 at GND, the output section is in the Frequency Modulation mode with non-overlapping conduction, which means that both ballast output drivers will be low during tDIS (Figure 2). In the overlapping mode (VCO-O), Pin 8 is left open and the transition from OUT A high to OUT B high occurs with no dead time. This mode is typically used in current fed ballast topologies.
VMUL 0.034 x I(SINE) x (VEA - 1.1 x (14k) )
(1)
where: I(SINE) is the current in the dropping resistor, V(EA) is the output of the error amplifier (Pin 20). The output of the gain modulator is limited to 0.88V. AVERAGE CURRENT AND OUTPUT VOLTAGE REGULATION The PWM regulator in the PFC Control section will act to offset the positive voltage caused by the multiplier output by producing an offsetting negative voltage on the current sense resistor at Pin 4. A cycle-by-cycle current limit is included to protect the MOSFET from high speed current transients. When the voltage at Pin 4 goes negative by more than 1V, the PFC cycle is terminated. For more information on compensating the average current and boost voltage error amplifier loops, see Application Note 16 .
R(X)/C(X) INTERRUPT VREF VCC VREF GND + + 11 OVP/INHIBIT + 5V 2 1 IA OUT IA - + - IA -1V + I(LIM) - 4 IA+/ I(LIM) 14K + - - 6.8V - PREHEAT AND INTERRUPT TIMER INH
12 10
+ -
LOGIC VCO-O PWM
MODE
8
LFB OUT UNDER-VOLTAGE AND THERMAL SHUTDOWN 2.6V - A1 OSCILLATOR CLK 2.5V LAMP F.B.
17 18 13
6 5
- +
R(SET) IR(SET) R(T)/C(T)
7
9
R S PFC OUT Q 16
VCO-O R I(SINE) GAIN MODULATORS + LFB OUT - EA VREF + - SQ OUT A PWM Q T Q OUT B 15
3
20 19
EA OUT EA -
14
Figure 1. ML4830 Block Diagram
6
ML4830
Mode
VCO VCO-O PWM
Pin 8
GND OPEN VREF
Definition
Frequency Modulation Overlapping VCO F.M. Pulse Width Modulation
Also, in both VCO modes, the when LFB OUT is high, ICHG = 0 and the minimum frequency occurs. The charging current varies according to two control inputs to the oscillator: 1. The output of the preheat timer 2. The voltage at Pin 6 (lamp current output) In preheat condition, charging current is fixed at
ICHG (PREHEAT ) = 2.5 R(SET)
Table 1. ML4830 Operating Modes OSCILLATOR In Table 1 above, the two VCO frequency ranges are controlled by the output of the LFB amplifier (Pin 6). As lamp current decreases, Pin 6 rises in voltage, causing the C(T) charging current to decrease, thereby causing the oscillator frequency to decrease. Since the ballast output network attenuates high frequencies, the power to the lamp will be increased. In PWM Mode, ICHG is 0 so the oscillator's frequency is set per (1) below.
(1)
In running mode, charging current decreases as the VPIN7 rises from 0V to VOH of trhe LAMP FB amplifier. The highest frequency will be attained when ICHG is highest, which is attained when VPIN6 is at 0V:
ICHG(0) = 5 R(SET)
(2)
The oscillator frequency is determined by the following equations:
FOSC = 1 t CHG + tDIS
18
VREF
VREF
(3)
R(T)
ICHG
CONTROL
and
6.25 + ICHG R T t CHG = R T CT In 3.75 + ICHG R T
R(T)/C(T) 9 1.25/3.75 C(T) 5 mA + -
(4)
The oscillator's minimum frequency is set when ICHG = 0 where:
FOSC 1 0.51x R T CT
(5)
This assumes that tCHG >> tDIS. Highest lamp power, and lowest output frequency are attained when VPIN6 is at its maximum output voltage (VOH).
CLOCK
In this condition, the minimum operating frequency of the ballast is set per (5) above.
tDIS tCHG
VTH C(T)
For the IC to be used effectively in dimming ballasts with higher Q output networks a larger CT value and lower RT value can be used, to yield a smaller frequency excursion over the control range (VPIN6). The discharge current is set to 5mA. Assuming that IDIS >> IRT:
tDIS(VCO) 490 x CT
(6)
VTL
Figure 2. Oscillator Block Diagram and Timing
7
ML4830
IC BIAS, UNDER-VOLTAGE LOCKOUT AND THERMAL SHUTDOWN The IC includes a shunt regulator which will limit the voltage at VCC to 13.5 (VCCZ). The IC should be fed with a current limited source, typically derived from the ballast transformer auxiliary winding. When VCC is below VCCZ - 0.7V, the IC draws less than 1.7mA of quiescent current and the outputs are off. This allows the IC to start using a "bleed resistor" from the rectified AC line.
VCCZ VCC V(ON) V(OFF)
This will produce a high frequency (or low duty cycle) for filament preheat, but will not produce sufficient voltage to ignite the lamp. After cathode heating, the inverter frequency drops to FMIN causing a high voltage to appear to ignite the lamp. If the voltage does not drop when the lamp is supposed to have ignited, the lamp voltage feedback coming into Pin 10 rises to above VREF, the C(X) charging current is shut off and the inverter is inhibited until C(X) is discharged by R(X) to the 1.2V threshold. Shutting off the inverter in this manner prevents the inverter from generating excessive heat when the lamp fails to strike or is out of socket. Typically this time is set to be fairly long by choosing a large value of R(X). LFB OUT is ignored until C(X) reaches 6.8V threshold. The lamps are therefore driven to full power and then dimmed. The C(X) pin is clamped to about 7.5V.
t 15mA
A timing diagram of lamp ignition and restart sequences provided by the circuit of Figure 4 is given in Figure 7.
ICC
1.3mA t
R(X)/C(X) .625 R(SET) 12 C(X) R(X) 6.8 + 1.2/6.8 - R 10 INT VREF - + Q S DIMMING LOCKOUT INHIBIT 1.2/3.4 + HEAT -
Figure 3. Typical VCC and ICC waveforms when ML4830 is started with a bleed resistor from the rectified AC line and bootstrapped from the ballast transformer. To help reduce ballast cost, the ML4830 includes a temperature sensor which will inhibit ballast operation if the IC's junction temperature exceeds 120C. In order to use this sensor in lieu of an external sensor, care should be taken when placing the IC to ensure that it is sensing temperature at the physically appropriate point in the ballast. The ML4830's die temperature can be estimated with the following equation:
TJ TA x PD x 65C / W
(7) Figure 4. Lamp Preheat and Interrupt Timers
STARTING, RE-START, PREHEAT AND INTERRUPT The lamp starting scenario implemented in the ML4830 is designed to maximize lamp life and minimize ballast heating during lamp out conditions. The circuit in Figure 4 controls the lamp starting scenarios: Filament preheat and Lamp Out interrupt. C(X) is charged
Mode
Preheat Dimming Lock-out Dimming Control
PWM
50% D(MAX)% 0 to D(MAX)%
FM
[F(MAX) to F(MIN)] 2 F(MIN) F(MIN) to F(MAX)
with a current of
IR(SET ) 4
or 0.625 and disch arg ed R(SET)
through R(X). The voltage at C(X) is initialized to 0.7V (VBE) at power up. The time for C(X) to rise to 3.4V is the filament preheat time. During that time, the oscillator
ch arg ing current (ICHG ) is 2.5 in both VCO mod es. R(SET)
Figure 5. Lamp Starting Summary A summary of the lamp starting scenarios are given in figure 5 for both PWM and Frequency Modulation modes. The PWM duty cycle is defined as:
Duty Cycle = t ON t CLK
8
ML4830
SEMI-STANDARD CAPABILITIES
tON(MAX) CLOCK
tCLK OUT A tON
The ML4830 is designed to work in a wide variety of electronic ballast applications. For high volume, cost sensitive applications, a ballast design can be implemented and debugged using the ML4830. From that design, Micro Linear can produce a reduced feature set, optimized ballast IC design quickly and easily with low risk. Contact your Micro Linear representative or call Micro Linear for more information on Semi-Standard options.
tON
OUT B
Figure 6. Definition of Duty Cycles
6.8 3.4 R(X)/C(X) 1.2 0.65 0 HEAT
DIMMING LOCKOUT
7.5 INT
INHIBIT
Figure 7. Lamp Starting and Restart Timing
9
6 15 14 13 12 11 7 8 9 10 R5 R24 C13 C6 C7 R15 C14 C15 C16
R2
R3
IC1
10
C22 D11 D3 + D7 T1 D9 C8 C10 C17 C11 C19 T4 R21 R22 C20 R11 R13 R19 + C24 Q3 + C9 Q1 R8 + R12 R20 T2 Q2 T5 C23 B B R D4 R6 R7 D8 D12 T3 Y
ML4830
F1
L1
APPLICATIONS
C1
D1
120V
Y R
C2
C3
-
D2
L2
D5
R1
D6
VCC R9 R10 C12 R14 1 20 19 18 17 16 R17 2 C5 3 4 5
D13 VCC
INHIBIT
C4
R18 D10 Dimming Control
R4
R23 C21
Figure. 8 Typical Application: 2-Lamp Isolated Dimming Ballast with Active Power Factor Correction for 120VAC Input
R16
ML4830
APPLICATIONS
(continued) The schematic (Figure 8) and the bill of materials on the following pages represents a complete parts list for the schematic (Figure 8). Designators refer to Micro Linear's "rev B" PCB.
TABLE 1: PARTS LIST FOR THE ML4830 TYPICAL APPLICATION
CAPACITORS QTY.
2 1 4 1 1 2 1 1 1 3 1 1 1 1 1
REF.
C1, 2 C3
DESCRIPTION
3.3nF, 125VAC, 10%, ceramic, "Y" capacitor 0.33F, 250VAC, "X", capacitor
MFR.
Panasonic Panasonic AVX AVX AVX AVX Panasonic Panasonic Panasonic AVX AVX WIMA WIMA AVX Panasonic
PART NUMBER
ECK-DNS332ME ECQ-U2A334MV SR215C104KAA SR211C472KAA RPE121COG152 SR305E105MAA ECE-A1EFS101 ECE-S2EG101E ECE-A50Z4R7 SR305C224KAA SR151V152KAA MKP10, 22nF, 630V, 5% MKP10, 0.1F, 250V, 5% SR211C103KAA ECE-A16Z220
C4, 8, 9, 12, 22 0.1F, 50V, 10%, ceramic capacitor C5 C6 C7 C10 C11 C13 C14, 15, 17 C16 C19 C20 C21 C24 47nF, 50V, 10%, ceramic capacitor 1.5F, 50V, 2.5%, NPO ceramic capacitor 1F, 50V, 20%, ceramic capacitor 100F, 25V, 20%, electrolytic capacitor 100F, 250V, 20%, electrolytic capacitor 4.7F, 50V, 20%, electrolytic capacitor 0.22F, 50V, 10%, ceramic capacitor 1.5F, 50V, 10%, ceramic capacitor 22nF, 630V, 5%, polypropylene capacitor 0.1F, 250V, 5%, polypropylene capacitor 0.01F, 50V, 10%, ceramic capacitor 220F, 16V, 20%, electrolytic capacitor
RESISTORS: 1 1 1 1 1 1 1 3 1 1 1 R1 R2 R3 R4 R5 R6 R7 R8, 22, 11 R9 R10, 13 R12, 20 0.5y, 5%, 1/2W, metal film resistor 4.3K, 1/4W, 5%, carbon film resistor 47K, 1/4W, 5%, carbon film resistor 12K, 1/4W, 5%, carbon film resistor 20K, 1/4W, 1%, metal film resistor 360K, 1/4W, 5%, carbon film resistor 36K, 1W, 5%, carbon film resistor 22y, 1/4W, 5%, carbon film resistor 402K, 1/4W, 1%, metal film resistor 17.8K, 1/4W, 1%, metal film resistor 475K, 1/4W, 1%, metal film resistor NTE Yageo Yageo Yageo Dale Yageo Yageo Yageo Dale Dale Dale 4.3K-Q 47K-Q 12K-Q SMA4-20K-1 360K-Q 36KW-1-ND 22-Q SMA4-402K-1 SMA4-17.8K-1 SMA4-475K-1
11
ML4830
TABLE 1: PARTS LIST FOR ML4830 TYPICAL APPLICATION
RESISTORS: (Continued) QTY.
4 1 1 1 1 1 R14 R15 R16, 19 R18 R21 R23
(Continued)
REF.
DESCRIPTION
100K, 1/4W, 5%, carbon film resistor 681K, 1/4W, 5%, carbon film resistor 10K, 1/4W, 1%, metal film resistor 4.7K, 1/4W, 5%, carbon film resistor 33y, 1/4W, 5%, carbon film resistor 25K, pot (for dimming adjustment)
MFR.
Yageo Yageo Dale Tageo Yageo Bourns
PART NUMBER
100K-Q 681K-Q SMA4-10K-1 681K-Q 33-Q 3386P-253-ND
DIODES: 4 2 1 6 IC's: 1 IC1 ML4830, Electronic Ballast Controller IC Micro Linear ML4830CP D1, 2, 3, 4 D5, 6 D7 D8, 9, 10, 11 12, 13 1A, 600V, 1N4007 diode (or 1N5061 as a substitute) 1A, 50V (or more), 1N4001 diodes 3A, 400V, BYV26C or BYT03 400 fast recovery or MUR440 Motorola ultra Fast diode 0.1A, 75V, 1N4148 signal diode Motorola Motorola GI Motorola 1N4007TR 1N4001TR BYV26C 1N4148TR
TRANSISTORS: 3 Q1, 2, 3 3.3A, 400V, IRF720 power MOSFET IR IR720
MAGNETICS: 1 T1 T1 Boost Inductor, E24/25, 1mH, Custom Coils P/N 5039 or Coiltronics P/N CTX05-12538-1 E24/25 core set, TDK PC40 material 8-pin vertical bobbin (Cosmo #4564-3-419), Wind as follows: 195 turns 25AWG magnet wire, start pin #1, end pin #4 1 layer mylar tape 14 turns 26AWG magnet wire, start pin #3, end pin #2 NOTE: Gap for 1mH 5% T2 Gate Drive Xfmr, LPRI = 3mH, Custom Coils P/N 5037 or Coiltronics P/N CTX05-12539-1 Toroid Magnetics YW-41305-TC Wind as follows: Primary = 25 turns 30AWG magnet wire, start pin #1, end pin #4 Secondary = 50 turns 30AWG magnet wire, start pin #5, end pin #8
1
T2
12
ML4830
TABLE 1: PARTS LIST FOR ML4830 TYPICAL APPLICATION
MAGNETICS: (Continued) QTY.
1 T3
(Continued)
REF.
DESCRIPTION
MFR.
PART NUMBER
T3 Inductor, LPRI = 1.66mH, Custom Ciols P/N 5041 or Coiltronics P/N CTX05-12547-1 E24/25 core set, TDK PC40 material 10 pin horizontal bobbin (Plastron #0722B-31-80) Wind as follows: 1st: 170T of 25AWG magnet wire; start pin #10, end pin #9. 1 layer of mylar tape 2nd: 5T of #32 magnet wire; start pin #2, end pin #1 1 layer of mylar tape 3rd: 3T of #30 Kynar coated wire; start pin #4, end pin #5 4th: 3T of #30 Kynar coated wire; start pin #3, end pin #6 5th: 3T of #30 Kynar coated wire; start pin #7, end pin #8 NOTE: Gap for 1.66mH 5% (pins 9 to 10) T4 Power Xfmr, LPRI = 3.87mH, Custom Ciols P/N 5038 or Coiltronics P/N CTX05-12545-1 E24/25 core set, TDK PC40 material 8 pin vertical bobbin (Cosmo #4564-3-419) Wind as follows: 1st: 200T of 30AWG magnet wire; start pin #1, end pin #4. 1 layer of mylar tape 2nd: 300T of 32AWG magnet wire; start pin #5, end pin #8 NOTE: Gap for inductance primary: (pins 1 to 4) @ 3.87mH 5% T5 Current Sense Inductor, Custom Coils P/N 5040 or Coiltronics P/N CTX05-12546-1 Toroid Magnetics YW-41305-TC Wind as follows: Primary = 3T 30AWG magnet coated wire, start pin #1, end pin #4 Secondary = 400T 35AWG magnet wire, start pin #5, end pin #8
1
T4
1
T5
INDUCTORS: 2 FUSES: 1 2 HARDWARE: 1 2 3 Single TO-220 Heatsink Double TO-220 Heatsink MICA Insulators Aavid Eng. IERC Keystone PB1ST-69 PSE1-2TC 4673K-ND F1 2A fuse, 5 x 20mm miniature Fuse Clips, 5 x 20mm, PC Mount Littlefuse F948-ND F058-ND L1, 2 EMI/RFI Inductor, 600H, DC resistance = 0.45y Prem. Magnetics SPE116A
13
ML4830
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P20 20-Pin PDIP
1.010 - 1.035 (25.65 - 26.29) 20
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.060 MIN (1.52 MIN) (4 PLACES)
1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
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ML4830
PHYSICAL DIMENSIONS
inches (millimeters)
Package: S20 20-Pin SOIC
0.498 - 0.512 (12.65 - 13.00) 20
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.007 - 0.015 (0.18 - 0.38)
ORDERING INFORMATION
PART NUMBER ML4830CP (EOL) ML4830CS (Obsolete) TEMPERATURE RANGE 0C to 85C 0C to 85C PACKAGE Molded PDIP (P20) Molded SOIC (S20)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. DS4830-01
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
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